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  1. MariaDB Server
  2. MDEV-28836

Correcting the cache alignment for Table_cache_instance.

Details

    Description

      Correcting the cache alignment for Table_cache_instance.

      • Size of Table_cache_instance is 224 (64 bits processor)
      • To avoid cache sharing padding of cacheline size was added.
        This padding fails to generate closet possible alignment
        and infact causes bloating with size = 352 (128 bytes cacheline)
      • Proposed patch ensure that structure is cache aligned.
        (will submit the patch through github).

      -----------
      With patch a marginal improvement is seen with multi-numa nodes though not significant to classify this as performance issue.

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          causes

          Bug - A problem which impairs or prevents the functions of the product. MDEV-29308 10.8.4 fails to build on OpenBSD

          • Blocker - Blocks development and/or testing work, production could not run.
          • Closed

          Activity

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            krunalbauskar Krunal Bauskar added a comment - - edited

            reduction in Lock_table_cache contention with the patch

            without patch:

            wait/synch/mutex/sql/LOCK_table_cache 333452.0811 259553191

            with patch:

            wait/synch/mutex/sql/LOCK_table_cache 212476.5164 259676376

            slight performance improvement was observed with 4 numa nodes. (check the attached graph)

            krunalbauskar Krunal Bauskar added a comment - - edited reduction in Lock_table_cache contention with the patch without patch: wait/synch/mutex/sql/LOCK_table_cache 333452.0811 259553191 with patch: wait/synch/mutex/sql/LOCK_table_cache 212476.5164 259676376 slight performance improvement was observed with 4 numa nodes. (check the attached graph)
            marko Marko Mäkelä added a comment -

            We assume at compilation time that the cache line size is 128 bytes on ARMv8 and POWER. On IBM s390 and s390x it is 256 bytes, and on x86 and AMD64 64 bytes.

            The suggested change would also reduce the memory footprint, because the padding between objects would be reduced.

            marko Marko Mäkelä added a comment - We assume at compilation time that the cache line size is 128 bytes on ARMv8 and POWER. On IBM s390 and s390x it is 256 bytes, and on x86 and AMD64 64 bytes. The suggested change would also reduce the memory footprint, because the padding between objects would be reduced.

            People

              marko Marko Mäkelä
              krunalbauskar Krunal Bauskar
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                Updated:
                Resolved:

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