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  1. MariaDB Server
  2. MDEV-26609

Avoid deriving ELEMENT_PER_LATCH from cacheline

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      Description

      • buffer pool has latches that protect access to pages.
      • there is a latch per N pages.
          (check page_hash_table for more details)
      • N is calculated based on the cacheline size.
      • for example: if cacheline size is
          : 64 then 7 pages pointers + 1 latch can be hosted on the same cacheline
          : 128 then 15 pages pointers + 1 latch can be hosted on the same cacheline
      • arm generally have wider cacheline so with arm 1 latch is used
          to access 15 pages vs with x86 1 latch is used to access 7 pages.
          Naturally, the contention is more with arm case.
      • said patch help relax this contention by limiting the elements
        per cacheline to 7 (+ 1 latch slot).
          for wider-cacheline (say 128), the remaining 8 slots are kept empty.
          this ensures there are no 2 latches on the same cacheline to avoid
        latch level contention.

      ----------
      Said patch has shown improvement in performance in range of 2-5%.

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              Assignee:
              marko Marko Mäkelä
              Reporter:
              krunalbauskar Krunal Bauskar
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