Uploaded image for project: 'MariaDB Server'
  1. MariaDB Server
  2. MDEV-26609

Avoid deriving ELEMENT_PER_LATCH from cacheline

Details

    Description

      • buffer pool has latches that protect access to pages.
      • there is a latch per N pages.
          (check page_hash_table for more details)
      • N is calculated based on the cacheline size.
      • for example: if cacheline size is
          : 64 then 7 pages pointers + 1 latch can be hosted on the same cacheline
          : 128 then 15 pages pointers + 1 latch can be hosted on the same cacheline
      • arm generally have wider cacheline so with arm 1 latch is used
          to access 15 pages vs with x86 1 latch is used to access 7 pages.
          Naturally, the contention is more with arm case.
      • said patch help relax this contention by limiting the elements
        per cacheline to 7 (+ 1 latch slot).
          for wider-cacheline (say 128), the remaining 8 slots are kept empty.
          this ensures there are no 2 latches on the same cacheline to avoid
        latch level contention.

      ----------
      Said patch has shown improvement in performance in range of 2-5%.

      Attachments

        Issue Links

          Activity

            patch submitted through the pr: https://github.com/MariaDB/server/pull/1910

            krunalbauskar Krunal Bauskar added a comment - patch submitted through the pr: https://github.com/MariaDB/server/pull/1910

            I see that the cache line size is 128 bytes also on POWER, and 256 bytes on s390x. I hope that danblack can assess the performance impact on those architectures.

            In 10.6, there is also lock_sys_t::hash_table::ELEMENTS_PER_LATCH that we may want to change in the same way.

            This change would not affect AMD64 or IA-32 or other systems where the cache line size is 64 bytes.

            marko Marko Mäkelä added a comment - I see that the cache line size is 128 bytes also on POWER, and 256 bytes on s390x. I hope that danblack can assess the performance impact on those architectures. In 10.6, there is also lock_sys_t::hash_table::ELEMENTS_PER_LATCH that we may want to change in the same way. This change would not affect AMD64 or IA-32 or other systems where the cache line size is 64 bytes.

            As suggested, I tried extending the patch to lock_sys::hash_table and continued to observe a performance difference. Improvement for read-write is 5-6%. Check the attached graph.

            krunalbauskar Krunal Bauskar added a comment - As suggested, I tried extending the patch to lock_sys::hash_table and continued to observe a performance difference. Improvement for read-write is 5-6%. Check the attached graph.

            People

              marko Marko Mäkelä
              krunalbauskar Krunal Bauskar
              Votes:
              0 Vote for this issue
              Watchers:
              2 Start watching this issue

              Dates

                Created:
                Updated:
                Resolved:

                Git Integration

                  Error rendering 'com.xiplink.jira.git.jira_git_plugin:git-issue-webpanel'. Please contact your Jira administrators.